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1 features ? serial peripheral interface (spi) compatible ? supports spi modes 0(0,0) and 3(1,1) ? low-voltage and standard-voltage operation C 5.0 (v cc = 4.5v to 5.5v) C 2.7 (v cc = 2.7v to 5.5v) C 1.8 (v cc = 1.8v to 3.6v) ? 2.1 mhz clock rate (5v) compatibility ? 8-byte page mode ? block write protection C protect 1/4, 1/2, or entire array ? write protect (wp ) pin and write disable instructions for both hardware and software data protection ? self-timed write cycle (10 ms max) ? high reliability C endurance: 1 million write cycles C data retention: 100 years C esd protection: >4000v ? automotive grade and extended temperature devices available ? 8-pin pdip and jedec soic packages description the at25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (eeprom) organized as 128/256/512 words of 8 bits each. the device is optimized for use in many industrial and commercial applica- tions where low power and low voltage operation are essential. the at25010/020/040 is available in space saving 8-pin pdip and 8-pin jedec (soic) packages. the at25010/020/040 is enabled through the chip select pin (cs ) and accessed via a 3-wire interface consisting of serial data input (si), serial data output (so), and serial clock (sck). all programming cycles are completely self-timed, and no sepa- rate erase cycle is required before write. block write protection is enabled by programming the status register with one of four blocks of write protection. separate program enable and program disable instruc- tions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts. the hold pin may be used to suspend any serial communication without resetting the serial sequence. spi serial eeproms 1k (128 x 8) 2k (256 x 8) 4k (512 x 8) at25010 at25020 at25040 rev. 0606eC08/98 spi, 1k serial e 2 prom pin configurations pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input 8-pin pdip 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-pin soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si
at25010/020/040 2 block diagram absolute maximum ratings* operating temperature ................................. -55c to + 125c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................... -65c to + 150c voltage on any pin with respect to ground ....................................-1.0v to + 7.0v maximum operating voltage........................................... 6.25v dc output current........................................................ 5.0 ma
at25010/020/040 3 note: 1. this parameter is characterized and is not 100% tested. notes: 1. this parameter is preliminary and atmel may change the specifications upon further characterization. 2. v il min and v ih max are reference only and are not tested. pin capacitance (1) applicable over recommended operating range from t a = 25c, f = 1.0 mhz, v cc = +5.0v (unless otherwise noted). test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6 pfv in = 0v dc characteristics applicable over recommended operating range from: t ai = -40c to +85c, v cc = +1.8v to +5.5v, t ac = 0c to +70c, v cc = +1.8v to +5.5v (unless otherwise noted). symbol parameter test condition min max units v cc1 (1) supply voltage 1.8 5.5 v v cc2 supply voltage 2.7 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v at 1 mhz, so = open 3.0 ma i cc2 supply current v cc = 5.0v at 2 mhz, so = open 6.0 ma i sb1 (1) standby current v cc = 1.8v cs = v cc 100 m a i sb2 standby current v cc = 2.7v cs = v cc 100 m a i sb3 standby current v cc = 5.0v cs = v cc 100 m a i il input leakage v in = 0v to v cc -0.6 3.0 m a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c-0.63.0 m a v il (2) input low voltage -0.6 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 4.5v v cc 5.5v i ol = 2.0 ma 0.4 v v oh1 output high voltage i oh = -1.0 ma v cc - 0.8 v v ol2 output low voltage 1.8v v cc 3.6v i ol = 0.15 ma 0.2 v v oh2 output high voltage i oh = -100 m av cc - 0.2 v
at25010/020/040 4 ac characteristics applicable over recommended operating range from t a = -40c to +85c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter voltage min max units f sck sck clock frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 2.1 2.1 0.5 mhz t ri input rise time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 m s t fi input fall time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 m s t wh sck high time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 800 ns t wl sck low time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 800 ns t cs cs high time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns t css cs setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns t csh cs hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns t su data in setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 50 100 ns t h data in hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 100 100 ns t hd hold setup time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 400 ns t cd hold hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 200 400 ns t v output valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 200 400 800 ns t ho output hold time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 ns
at25010/020/040 5 note: 1. this parameter is characterized and is not 100% tested. t lz hold to output low z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 100 100 100 ns t hz hold to output high z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 100 ns t dis output disable time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 500 1000 ns t wc write cycle time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 10 ms endurance 5.0v, 25 c, page mode 1m write cycles ac characteristics (continued) applicable over recommended operating range from t a = -40c to +85c, v cc = as specified, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter voltage min max units
at25010/020/040 6 serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25010/020/040 always operates as a slave. transmitter/receiver: the at25010/020/040 has separate pins designated for data transmission (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. the op-code also contains address bit a8 in both the read and write instructions. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25010/020/040, and the serial output pin (so) will remain in a high impedance state until the falling edge of cs is detected again. this will reini- tialize the serial communication. chip select: the at25010/020/040 is selected when the cs pin is low. when the device is not selected, data will not be accepted via the si pin, and the serial output pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25010/020/040. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the write protect pin (wp ) will allow normal read/write operations when held high. when the wp pin is brought low, all write operations are inhibited. wp going low while cs is still low will interrupt a write to the at25010/020/040. if the internal write cycle has already been initiated, wp going low will have no effect on any write operation. spi serial interface
at25010/020/040 7 functional description the at25010/020/040 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6805 and 68hc11 series of microcontrollers. the at25010/020/040 utilizes an 8-bit instruction register. the list of instructions and their operation codes are con- tained in table 1. all instructions, addresses, and data are transferred with the msb first and start with a high-to-low cs transition. note: a represents msb address bit a8. write enable (wren): the device will power up in the write disable state when v cc is applied. all program- ming instructions must therefore be preceded by a write enable instruction. the wp pin must be held high during a wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the write disable instruction disables all programming modes. the wrdi instruction is independent of the status of the wp pin. read status register (rdsr): the read status register instruction provides access to the status register. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. these bits are set by using the wrsr instruc- tion. write status register (wrsr): the wrsr instruction allows the user to select one of four levels of protection. the at25010/020/040 is divided into four array segments. top quarter (1/4), top half (1/2), or all of the memory segments can be protected. any of the data within any selected segment will therefore be read only. the block write protection levels and corresponding status reg- ister control bits are shown in table 4. the two bits, bp1 and bp0 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. wren, t wc , rdsr). read sequence (read): reading the at25010/020/040 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select a device, the read op-code (including a8) is trans- mitted via the si line followed by the byte address to be read (a7-a0). upon completion, any data on the si line will be ignored. the data (d7-d0) at the specified address is then shifted out onto the so line. if only one byte is to be read, the cs line should be driven high after the data comes out. the read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. when the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one con- tinuous read cycle. table 1. instruction set for the at25010/020/040 instruction name instruction format operation wren 0000 x110 set write enable latch wrdi 0000 x100 reset write enable latch rdsr 0000 x101 read status register wrsr 0000 x001 write status register read 0000 a011 read data from memory array write 0000 a010 write data to memory array table 2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 xxxxbp1bp0wenrdy table 3. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 4. bit 3 (bp1) see table 4. bits 4-7 are 0s when device is not in an internal write cycle. bits 0-7 are 1s during an internal write cycle. table 4. block write protect bits level status register bits array addresses protected bp1 bp0 at25010 at25020 at25040 0 0 0 none none none 1 (1/4) 0 1 60-7f c0-ff 180-1ff 2 (1/2) 1 0 40-7f 80-ff 100-1ff 3 (all) 1 1 00-7f 00-ff 000-1ff
at25010/020/040 8 write sequence (write): in order to program the at25010/020/040, the write protect pin (wp ) must be held high and two separate instructions must be executed. first, the device must be write enabled via the write enable (wren) instruction. then a write (write) instruction may be executed. also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. during an internal write cycle, all commands will be ignored except the rdsr instruction. a write instruction requires the following sequence. after the cs line is pulled low to select the device, the write op-code (including a8) is transmitted via the si line fol- lowed by the byte address (a7-a0) and the data (d7-d0) to be programmed. programming will start after the cs pin is brought high. (the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit. the ready/busy status of the device can be determined by initiating a read status register (rdsr) instruc- tion. if bit 0 = 1, the write cycle is still in progress. if bit 0 = 0, the write cycle has ended. only the read status register instruction is enabled during the write pro- gramming cycle. the at25010/020/040 is capable of an 8-byte page write operation. after each byte of data is received, the three low order address bits are internally incremented by one; the six high order bits of the address will remain con- stant. if more than 8 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. the at25010/020/040 is automati- cally returned to the write disable state at the completion of a write cycle. note: if the wp pin is brought low or if the device is not write enabled (wren), the device will ignore the write instruc- tion and will return to the standby state, when cs is brought high. a new cs falling edge is required to re-ini- tiate the serial communication.
at25010/020/040 9 timing diagrams synchronous data timing (for mode 0) wren timing wrdi timing so v oh v ol hi-z hi-z t v valid in si v ih v il t h t su t dis sck v ih v il t wh t csh cs v ih v il t css t cs t wl t ho
at25010/020/040 10 rdsr timing wrsr timing read timing cs sck 01234567891011121314 si instruction so 76543210 data out msb high impedance cs sck 01234567891011121314 si instruction so 76543210 data in high impedance 15
at25010/020/040 11 write timing hold timing cs sck 01234567891011121314 si instruction so 76543210 data in high impedance 15 16 17 18 19 20 21 22 80 1 2 3 4 5 6 7 9th bit of address 23 byte address so sck hold t cd t hd t hz t lz t cd t hd cs
at25010/020/040 12 package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) options blank standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 5.5v) at25010 ordering information t wp (max) (ms) i cc (max) ( m a) i sb (max) ( m a) f max (khz) ordering code package operation range 10 6000 100 2000 at25010-10pc at25010-10sc 8p3 8s1 commercial (0 c to 70 c) 100 2000 at25010-10pi at25010-10si 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 1000 at25010-10pc-2.7 at25010-10sc-2.7 8p3 8s1 commercial (0 c to 70 c) 100 1000 at25010-10pi-2.7 at25010-10si-2.7 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 500 at25010-10pc-1.8 at25010-10sc-1.8 8p3 8s1 commercial (0 c to 70 c) 100 500 at25010-10pi-1.8 at25010-10si-1.8 8p3 8s1 industrial (-40 c to 85 c)
at25010/020/040 13 at25020 ordering information t wp (max) (ms) i cc (max) ( m a) i sb (max) ( m a) f max (khz) ordering code package operation range 10 6000 100 2100 at25020-10pc at25020n-10sc 8p3 8s1 commercial (0 c to 70 c) 100 2100 at25020-10pi at25020n-10si 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 2100 at25020-10pc-2.7 at25020n-10sc-2.7 8p3 8s1 commercial (0 c to 70 c) 100 2100 at25020-10pi-2.7 at25020n-10si-2.7 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 500 at25020-10pc-1.8 at25020n-10sc-1.8 8p3 8s1 commercial (0 c to 70 c) 100 500 at25020-10pi-1.8 at25020n-10si-1.8 8p3 8s1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) options blank standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 5.5v)
at25010/020/040 14 at25040 ordering information t wp (max) (ms) i cc (max) ( m a) i sb (max) ( m a) f max (khz) ordering code package operation range 10 6000 100 2100 at25040-10pc at25040n-10sc 8p3 8s1 commercial (0 c to 70 c) 100 2100 at25040-10pi at25040n-10si 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 2100 at25040-10pc-2.7 at25040n-10sc-2.7 8p3 8s1 commercial (0 c to 70 c) 100 2100 at25040-10pi-2.7 at25040n-10si-2.7 8p3 8s1 industrial (-40 c to 85 c) 10 3000 100 500 at25040-10pc-1.8 at25040n-10sc-1.8 8p3 8s1 commercial (0 c to 70 c) 100 500 at25040-10pi-1.8 at25040n-10si-1.8 8p3 8s1 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline package (jedec soic) options blank standard device (4.5v to 5.5v) -2.7 low voltage (2.7v to 5.5v) -1.8 low voltage (1.8v to 5.5v)
at25010/020/040 15 packaging information .400 (10.16) .355 (9.02) pin 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) .300 (7.62) ref .210 (5.33) max seating plane .100 (2.54) bsc .015 (.380) min .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62) 0 15 ref .430 (10.9) max .012 (.305) .008 (.203) .020 (.508) .013 (.330) pin 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) bsc .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 0 8 ref .010 (.254) .007 (.203) .050 (1.27) .016 (.406) 8p3 , 8-lead, 0.300" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-001 ba 8s1 , 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) dimensions in inches and (millimeters)

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